The invention relates to prepreg sheets useful as a dielectric layer in an integrated circuit element.
Integrated circuit geometries, over time, have become smaller and smaller. As a result, the density of the element packaging has become higher and higher. The evolution in packaging has been from printed wiring boards to thick film multilayer ceramics to thin multilayer polymers, as well as multilayer ceramic in combination with thin multilayer polymers, the latter being perhaps 60 times better than printed wiring boards in terms of size to weight ratio, power delays, relative cost, density and time delay.
For thin film multilayer polymers, the ideal polymer would have a low dielectric constant, low thermal expansion, good physical properties such as high elongation and high fracture toughness, good adhesion, low water absorption, thermal stability to 400.degree. C. and low solvent absorption. It must be processible so as to produce thin, pinhole-free layers. At present, the polymer of choice is a polyimide and the conventional process employs spinning of the polymer (dissolved in a solvent) on a rotating wafer substrate to form a film. This process is discussed, for example, in Betram, W. J., Jr., "High-Density, Large Scale Interconnection for Improved VLSI System Performance", Proceedings of the IEDM-International Electron Devices Meeting, Washington, D. C., Dec. 6-9, 1987.
The requirements for the interlevel dielectric layers are that the material have as low a dielectric constant as possible, that the material planarize as much as possible the structure of the underlying conductor levels and that processes exist to define the vias which interconnect the levels of metallization. The material of choice is a commercialy available polyimide.
The polyimide material is applied using spinning techniques in commercial equipment developed for the application of photoresistant material. The desired thicknesses of 5 micrometers and 10 micrometers are obtainable and the top surface meets the requirements for planarity by this method. Polymers suitable for application by this process include the PYRALIN.RTM. family of polyimides available from DuPont, as well as similar polymers available from others. These are all condensation polymers. Dow Chemical Co. markets a polymer, Benzocyclobutene, used for the same applications sold under the trademark BCB which is an addition reaction polymer. The polymer in solution is puddled onto a wafer and spun, typically at 5000 rpm for 30 seconds, resulting in air drying of the material. Polymer properties and processing details are available in the product information brochures produced by DuPont, e.g., "PYRALIN.RTM. LX Processing Guidelines", May 17, 1988.
In the spinning process, up to 90-95% of the polymer solution is wasted by being spun off of the spinning wafer due to centrifugal force effects. These coating materials presently typically cost one dollar per gram of material, resulting in huge waste expenses to produce quite thin coatings.
Advantages of the currently used process and product include a dielectric constant ranging from 2.7 to 3.5, good thermal stability to 400.degree. C. and low thermal expansion. Disadvantages include the high cost of coatings and the low material utilization due to spinning. Many spinning steps are required and the rheology of the polymer solutions is the critical process control variable.
A printed circuit board base prepreg material is disclosed in U.S. Pat. No. 4,772,509. That reference discloses a printed circuit board base prepreg material of a porous, expanded polytetrafluoroethylene (PTFE) membrane or fabric impregnated with a polyimide resin varnish. Upon curing, a printed circuit board base material of porous, expanded PTFE impregnated with polyimide resin is provided. The base material of the invention may be laminated to a glass fabric to improve strength and dimensional stability.
See, also, Chao, Clinton C., et al, "Multilayer Thin-Film Substrate for Multichip Packaging", Proceedings of the 38th Electronic Components Conference, 1988, IEEE.
By definition, the term "planarity" as used herein is defined as the ratio of the height of the dielectric at a point where there is no feature underneath the layer divided by the height of the dielectric over a feature, including the thickness of the feature. The feature thickness is less than 50% of the dielectric thickness when the dielectric is measured at a point without a feature. Thus, a perfectly flat dielectric would have a planarity of 1.0 and a perfectly conformal coating where the feature thickness is 50% of the dielectric thickness plus the feature thickness would have a planarity of 0.5.
In a sequentially constructed, high-density interconnect, i.e., any conductive network between the outside world and devices on the integrated circuit that are defined by high resolution photo imaging, planarity is a critical variable for producing reliable electrical interconnects. The dielectric must encapsulate the signal lines of a previous layer while providing a nearly flat surface for imaging the next signal layer. The reason that this flatness is required is two-fold. First, the equipment for imaging fine lines exists currently in the semiconductor industry. This equipment can achieve very fine line resolution but requires a flat surface due to a very short focal length. Therefore, if the surface is not highly planar, line geometries cannot be controlled accurately, and, in the worst case, lines may disappear causing unwanted opens (shorts), resulting in failures. Second, a high degree of planarity is required for impedance control. The spacing between signal and ground must remain constant along a signal path. Failure to do so can result in signal transmissions of poor quality.